SAR ADC in 22 nm FDSOI
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Successive Approximation (SAR) Analog-to-Digital Converters (ADCs) are among themost energy efficient ADCs and has therefore received enormous attention in medical andwireless applications. The great energy efficiency of SAR ADCs are mainly attributed tothe downscaling of Complementary Metal-Oxide-Semiconductor (CMOS) circuits, sincethe SAR architecture benefits greatly by going to smaller and smaller CMOS processnodes. Due to this excellent scaling, the introduction of smaller CMOS nodes opens upfor new opportunities and challenges when designing SAR ADCs. In this thesis, the speed limits of SAR ADCs have been pushed, while high resolutionand energy efficiency are maintained. The SAR designed in this thesis is a Nyquist ADCintended for medical ultrasound applications and is designed in a 22 nm Fully DepletedSilicon-On-Insulator (FDSOI) process. The designed SAR ADC is simulated post-layoutand the mean Monte Carlo results yields an Effective Number of Bits (ENOB) of 10.2 bitsat a sample rate of 100 MS/s. The power consumption is 268 μW and the resulting meanMonte CarloWalden Figure of Merit (FoM) for the ADC is 2.29 fJ/conv.-step. This is currentlybetter than all state-of-the-art ADCs with similar specifications. The ADC designedis also unique in the sense that no one else has managed similar speed and resolution withthe same simple pure SAR ADC architecture. These results are accomplished by using a popular dynamic latch comparator with capacitiveloading, improving on already existing bootstrapped switch topology, improvementon already existing Capacitive Digital-to-Analog Converter (CDAC) architecture to greatlyincrease linearity and still achieve small unit capacitance, a custom made digital circuitrythat has very low propagation delay and clock generation based on CDAC bottom plate.