## Implementation of Empirical Mode Decomposition on an FPGA using Fixed Point Arithmetic

##### Master thesis

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http://hdl.handle.net/11250/2467028##### Issue date

2017##### Metadata

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##### Abstract

This report will test how well the empirical mode decomposition (EMD) algorithm performs on a field-programmable gate array (FPGA), using solely fixed point arithmetic. The implementation is designed to receive a data set of N 16 bits data points, and return the different intrinsic mode function (IMF) components and the residue. The implementation is based on the naive EMD, using cubic spline interpolation to generate the envelopes when finding the different IMF components. With fixed point precision, there will be a certain error when storing a decimal number. By applying precision bits, effectively multiplying the number by a factor of 2 for every bit applied, this error decreases. The implementation is designed to be able to specify the amount of precision bits wanted for the cubic spline calculations, with a maximum amount of 22. The implementation is simulated and tested for different amount of bits, and the resulting IMF components are compared to software implementation results using floating point precision. For a data set containing 2048 samples of uniform distributed noise, the number of precision bits would need to be greater than 13. Fewer precision bits did not produce any meaningful result due to the error for the later IMF component being too large. The error is defined as the difference between the floating point, and the fixed point precision results. This error is compared to the floating point precision to gain a signal to noise ratio (SNR). For every new IMF extracted, the SNR decreases. The main reason for this, is because the cubic splines are made out of third order polynomials, which also applies to the error. This means that the error would escalate quickly when the distance between the extrema becomes large. This results in more precision bits needed for later IMF components, in order to keep the SNR constant. For real-time purposes, the input signal sampling frequency for this design can not be higher than 159kHz for N = 2048. This sampling frequency becomes less for bigger window size, N, which was expected due to the complexity of the EMD algorithm.