Design and analysis of a video scaler suited for FPGA implementation
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A video scaler, is a module that receives a picture, enlarge or shrink it, and sends it back.The video scaler in this thesis was made to be part of an AXI-Stream Video System thatis suited to be implemented on a FPGA.The system is divided into three parts: the video scaler module, the video module andthe communication module, where the final goal was to use the communication mod-ule to send data from memory, to the video scaler, scale the video up or down, send iteither back to memory or to the video module where it could be displayed on a screenby HDMI/VGA.In the video scaler, an algorithm was used to scale up the images by a factor of 4. Thescaler needs to know the pixel-width and pixel-height of the image prior to the scalingto prevent the scaled image from being distorted or askewed. Width and height caneasily be configured to fit new images.For the downscaling, a form of merging was used to scale down by a factor of 4. It wastested on the same images as the upscaler, and both of the scalers use the same inter-faces since they have to fit into the AXI-Stream Video System.The downscaler was simulated and implemented into a system where it communicatedwith memory, which was running on the FPGA, while the upscaler was only simulated.