Design of a residue amplifier for a SAR-assisted pipeline ADC
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This thesis explores the use of the ring amplifier in 28 nm FDSOI. The intended use is asa residue amplifier in a SAR (successive approximation register) assisted pipeline ADC.The specifications for the ADC are 13 effective bits at a sampling rate of 50 MS/s. Thisthesis is a continuation of Sivert Krøvel s thesis work from 2016, where he used SARVerilogA-models and an ideal amplifier. This thesis continues to use the SAR-models, butthe amplifier is replaced. The ring amplifier is a relatively new amplifier topology thattakes advantage of time domain properties to achieve higher speed and energy efficiencythan it is possible to reach using traditional operational amplifiers.This project does not manage to create an amplifier that meets the specifications, due toissues regarding noise and speed. The amplifier along with the ADC models gives 10.3effective bits at a sampling rate of 10 MS/s.