Analysis and Visualisation of Clock Tree Power in a full-chip-design
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In this thesis a tool to graph power density in a chip by combining placement data with power estimation results has been made for Nordic Semiconductor. The goal was to utilize the data generation power of the power estimation tool, preserving the detail of the data instead of looking at averages and totals. Extra focus was put on displaying power from clock trees, as they are generated in a part of the design process where power estimation data based on placement and routing is available. This thesis presents results from a tool able to graph power consumption over the chip area, a feature not seen in commercial tools. A thorough description of the features, how they were obtained and why they were needed is also included. The tool was developed with continuous feedback from the engineers that will be using it. It was implemented in the design phase for Nordic Semiconductor chip currently in progress to gain insight in the clock trees. The tool showed that several test benches used for estimating clock power were in fact printing the exactly the same output, meaning they were redundant. The tool transform power estimation reports to frames optimized to be joined together for animations. It can process reports with an average run time of 1.5 seconds per report when each report contains 40 000 cells. Rendering each frame takes an average of 2.1 seconds. The tool helps the designer to gather information on ineffective layout in reports that were previously deemed too large to be useful. Visualizing data over the chip surface shows rich information in a intuitive way, which can be useful for other domains.