Reliability of High Speed Ultra Low Voltage Differential CMOS Logic
Journal article, Peer reviewed
MetadataShow full item record
Original versionCircuits and Systems 2015, 6(5):121-135 10.4236/cs.2015.65013
In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.