Checking of Nanoscale Transistor Models
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A device compact model is a mathematical description of a device, e.g. a transistor, in anintegrated circuit. Compact models are designed to be a part of a larger simulation, andwork together with a circuit model. For this reason errors in the device model will multiplythroughout the simulation. Device model validation is thus an important prerequisite forsimulating integrated circuits. In this thesis a comprehensive set of qualitative benchmarktests is developed and presented. In the course of device model testing, several hundred curves can be produced and haveto be evaluated in terms of whether they behave as expected from the laws of physics. Tofacilitate this process a program that finds discontinuities in curves was implemented forthis thesis.