Ultra-Low Power SAR-ADC in 28nm CMOS Technology
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This thesis presents an improved ultra-low power 10-bit 1 kS/s successive approximation (SAR) analog to digital converter (ADC) building on the work performed by Simon Josepshen in 2013. The improved ADC has a supply of 450mV and operates at almost half the power consumption of previous work; achieving a consumption of 691.5 pW in post-layout simulation. This is possibly the best power consumption found in available literature. Higher resolution and lower power consumption is achieved with incremental changes to the original design and by exploiting the benefits of new technology. The design differs from the previous in some key ways; having a different comparator topology, different switching procedure and asynchronous operation. The effective resoultion is found to be around 9.4-bit, giving a figure of merit of 1.0 fJ/conversion-step.