3D Perspective Video Scaling Effects on FPGA
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The goal of this thesis was to design a video scaler able to do a perspective transform on a video stream. The scaler should be designed in VHDL and for FPGA, and the implementation should focus on achieving a low area while still doing a visually pleasing transformation. Additionally, the circuit should be able to operate in real time on high resolution video.The thesis continues the work carried out in a pre-project on the same topic. There, several algorithms were introduced and implemented in Matlab. The thesis is also inspired by a state of the art polyphase scaler able to scale between rectangular video, which is implemented in VHDL.Before the hardware unit was designed, software models of the relevant algorithms was created in Matlab. These models were used to compare the algorithms, and later to verify the hardware implementation. The comparison shows that some of the algorithms give high quality output, but are complex to design, and others give a lower visual quality for a much simpler implementation. This gives much flexibility to adapt the system to the resources available.To focus on the core functionality, the simplest set of algorithms were chosen for the hardware implementation. This was implemented in VHDL and tested and synthesised. During testing, two bugs were found, one in the calculation of perspective factors, used to tune the transform, and one affecting the last two columns off the output frame. The first error only affects the initialization of the module from software. The second affects visual quality, and needs further investigation. Apart from these errors, the design fulfills the requirements.Additionally, the synthesis revealed that the design takes up very few logic elements.