System Architecture of Digital Command Receivers for Space Applications
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Since its invention, the use of a phase locked loop (PLL) for demodulation of residual carrier phase and frequency modulated signals has been common practice as it is a good approximation of the ideal demodulator. The well known threshold effect of the ideal demodulator does not prevent it from being utilized even in systems designed for reception of weak signals such as satellite receivers.This report shows that a correlator demodulator can be implemented in the discrete domain that, for low carrier-to-noise ratios, achieves a better signal-to-noise ratio at the output than the ideal arctan phase detector, and thus a lower bit error rate in the subsequent BPSK demodulation.In addition to the enhanced performance in heavy noise, the demodulator structure can tolerate a small residual frequency offset, whereas the PLL has to be perfectly synchronized. This both relaxes the demands for the frequency correction circuitry, and reduces acquisition time in the presence of an initial frequency error.The correlator structure has strong similarities with a Costas receiver for general DSB-SC modulated signals resulting in an efficient implementation of a combined receiver for PM, FM and QAM/mPSK modulated signals.It is shown that the differentiator based Quadricorrelator has a very favorable performance for frequency difference detection compared to differentiation of the output of an ideal phase detector. If the differentiator based Quadricorrelator is to be used as a demodulator for wide-band frequency modulation, differentiators based on 4th order Lagrange polynomials allow for an efficient implementation while resulting in a substantial reduction of harmonic distortion compared with a simple three point differentiator.It is shown that converting from a single stage polyphase decimator to a multistage decimator consisting of a CIC stage and a polyphase stage may result in a substantial reduction in multiplication rate for a comparable performance. This may prove beneficial for FPGA s or general purpose processors without dedicated hardware multipliers.