FPGA Implementation of a Video Scaler
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Three algorithms for video scaling were developed and tested in software, for implementation on an FPGA. Two of the algorithms were implemented in a video scaler system. These two algorithms scale up with factors 1.25 and 1.875, which is used for scaling SD WIDE to HD resolution and SD WIDE to FullHD resolution, respectively. An algorithm with scaling factor 1.5, scaling HD to FullHD, was also discussed, but not implemented. The video scaler was tested with a verilog testbench provided by ARM. When passing the testbench, the video scaler system was loaded on an FPGA. Results from the FPGA were compared with the software algorithms and the simulation results from the testbench. The video scaler implemented on the FPGA produced predictable results. Even though a fully functional video scaler was made, there were not time left to create the necessary software drivers and application software that would be needed to run the video scaler in real time with live video output. So a comparison of the output from the implemented algorithms is performed with common scaling algorithms used in video scalers, such as bilinear interpolation and bicubic interpolation. This thesis also deal with graphics scaling. Some well-known algorithms for graphic scaling were written in software, including a self-made algorithm to suit hardware. These algorithms were not implemented in hardware, but comparison of the results are performed.