Processing Core for Compressing Wireless Data: The Enhancement of a RISC Microprocessor
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This thesis explores the ability of the proprietary Texas Instruments embedded 16 bits RISC microprocessor, NanoRisc, to process common lossless compression algorithms, and propose extensions in order to increase its performance on this task. In order to measure performance of the NanoRisc microprocessor, the existing software tool chain was enhanced for profiling and simulating the improvements, and three fundamentally different adaptive data compression algorithms with different supporting data structures were implemented in the NanoRisc assembly language. On the background of profiling results, some enhancements were proposed. The new enhancements improved throughput of the three implemented algorithms by between 18% and 103%, and the code sizes decreased between 6% and 31%. The bit field instructions also reduced RAM access by up to 53%. The enhancements were implemented in the NanoRisc VHDL model and synthesized. Synthesis reports showed an increase in gate count of 30%, but the whole NanoRisc core is still below 7k gates. Power consumption per MIPS increased by 7%, however reduced clock cycle count and memory access decreased the net power consumption of all tested algorithms. It is also shown that data compression with the NanoRisc prior to transmission in a low power RF transceiver may increase battery lifetime 4 times. Future work should include a comprehensive study of the effect of the proposed enhancements to more common applications for the NanoRisc microprocessor.