Accurate Delay Test of FPGA Routing Network by Branched Test Paths
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This Master s thesis documents a new test method for detection of small delay faults in FPGA routing network. The main purpose of the test is accurate detection of faults in all parts of the network. The second aim is minimizing test application time. The work of the thesis consisted of four parts. First, a literature study was performed to get background knowledge of FPGA architecture and basics of testing. Second, detection accuracy was defined and measured in SPICE for test paths with different number of fan-out. Third, test configurations were developed. And finally, detection accuracies for the proposed test method were calculated. The SPICE measurements were performed on an interconnect model of FPGA. They revealed that detection accuracy of defects tested by branches of a test path is less than detection accuracy of defects tested by stems of a test path. In addition, it was observed that detection accuracy is best in the beginning of a test path. In the proposed test method detection accuracy is improved by testing all segments outside switch matrices by test path stems, and applying test patterns to all bidirectional segments in both directions. A comparison to two previous test methods showed that the proposed test method is more accurate while keeping the same number of test configurations. The detection accuracy can be improved further by allowing more test configurations.