Fractional-n Frequency Synthesis
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A high level model of a fractional-n frequency synthesizer has been created in VHDLAMS, and simulations shows that the system works as intended. A voltage controlled oscillator has been designed at transistor level, and verified by simulations. Co-simulation has also been performed to verify that the high level model of the voltage controlled oscillator behaves similar to the transistor level design. The frequency synthesizer has a 3–30MHz input clock, and a 48–250MHz output clock. The output clock frequency is given by the input frequency multiplied by a fractional number, f_o = f_i * (n + K/M). The analysis has however revealed that the input clock must be divided down in order to get an acceptable loop filter size. It has been shown that a third order single loop error feedback modulator with initial condition, provides smooth noise shaping without spurious tones. The loop filter size is of great concern, and further work should be put into reducing its physical size. The on-chip resistor used to convert the control voltage to a tuning current for the oscillator have too large process variations, and the possibility of on-chip calibration should be investigated.